Yasue Yamamoto, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa, Hiroyuki Yamauchi. A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. IEICE Transactions, 90-C(5):1129-1137, 2007. [doi]
@article{YamamotoSKNSAKY07,
title = {A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI},
author = {Yasue Yamamoto and Masanori Shirahama and Toshiaki Kawasaki and Ryuji Nishihara and Shinichi Sumi and Yasuhiro Agata and Hirohito Kikukawa and Hiroyuki Yamauchi},
year = {2007},
doi = {10.1093/ietele/e90-c.5.1129},
url = {http://dx.doi.org/10.1093/ietele/e90-c.5.1129},
tags = {architecture, type system, logic, design},
researchr = {https://researchr.org/publication/YamamotoSKNSAKY07},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {90-C},
number = {5},
pages = {1129-1137},
}