A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design - researchr publication authors

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Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada. A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design. In José E. Franca, Rudolf Koch, editors, ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003. pages 189-192, IEEE, 2003. [doi]

This author has not been identified. Look up 'Hiroaki Yamaoka' in GoogleThis author has not been identified. Look up 'Makoto Ikeda' in GoogleThis author has not been identified. Look up 'Kunihiro Asada' in Google

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