Parallel Efficient Hierarchical Algorithms for Module Placement of Large Chips on Distributed Memory Architectures - researchr publication authors

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Laurence Tianruo Yang. Parallel Efficient Hierarchical Algorithms for Module Placement of Large Chips on Distributed Memory Architectures. In 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 22-25 September 2002, Warsaw, Poland. pages 405-408, IEEE Computer Society, 2002. [doi]

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