Laurence Tianruo Yang. Parallel Efficient Hierarchical Algorithms for Module Placement of Large Chips on Distributed Memory Architectures. In 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 22-25 September 2002, Warsaw, Poland. pages 405-408, IEEE Computer Society, 2002. [doi]
@inproceedings{Yang02:22,
title = {Parallel Efficient Hierarchical Algorithms for Module Placement of Large Chips on Distributed Memory Architectures},
author = {Laurence Tianruo Yang},
year = {2002},
url = {http://csdl.computer.org/comp/proceedings/parelec/2002/1730/00/17300405abs.htm},
tags = {architecture},
researchr = {https://researchr.org/publication/Yang02%3A22},
cites = {0},
citedby = {0},
pages = {405-408},
booktitle = {2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 22-25 September 2002, Warsaw, Poland},
publisher = {IEEE Computer Society},
isbn = {0-7695-1730-7},
}