Zong-Han Yang, Tsung-Yi Ho. Timing-aware clock gating of pulsed-latch circuits for low power design. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013. pages 1-4, IEEE, 2013. [doi]
@inproceedings{YangH13-17,
title = {Timing-aware clock gating of pulsed-latch circuits for low power design},
author = {Zong-Han Yang and Tsung-Yi Ho},
year = {2013},
doi = {10.1109/VLDI-DAT.2013.6533819},
url = {http://dx.doi.org/10.1109/VLDI-DAT.2013.6533819},
researchr = {https://researchr.org/publication/YangH13-17},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4435-7},
}