Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder

Lei Yang, Hui Liu, C.-J. Richard Shi. Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder. IEEE Trans. on Circuits and Systems, 53(4):892-904, 2006. [doi]

Abstract

Abstract is missing.