Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan. Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. In 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA. pages 398-403, IEEE Computer Society, 2007. [doi]
Abstract is missing.