VLSI architecture design for a fast parallel label assignment in binary image

Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang P. Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu. VLSI architecture design for a fast parallel label assignment in binary image. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 2393-2396, IEEE, 2005. [doi]

Authors

Shyue-Wen Yang

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Ming-Hwa Sheu

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Hsien-Huang P. Wu

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Hung-En Chien

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Ping-Kuo Weng

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Ying-Yih Wu

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