A PVT Tolerant sub-mA PLL in 65nm CMOS process - researchr publication authors

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Yi Yang, Liqiong Yang, Zhuo Gao. A PVT Tolerant sub-mA PLL in 65nm CMOS process. In 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008. pages 998-1001, IEEE, 2008. [doi]

This author has not been identified. Look up 'Yi Yang' in GoogleThis author has not been identified. Look up 'Liqiong Yang' in GoogleThis author has not been identified. Look up 'Zhuo Gao' in Google

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