Jinghao Ye, Masao Yanagisawa, Youhua Shi. A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing. In 2019 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019, Bangkok, Thailand, November 11-14, 2019. pages 29-32, IEEE, 2019. [doi]
Abstract is missing.