Anitha Kumari Yella, Gunturi Srivatsa, Carl Sechen. Are standalone gate size and VT optimization tools useful?. In 30th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2017, Windsor, ON, Canada, April 30 - May 3, 2017. pages 1-6, IEEE, 2017. [doi]
@inproceedings{YellaSS17,
title = {Are standalone gate size and VT optimization tools useful?},
author = {Anitha Kumari Yella and Gunturi Srivatsa and Carl Sechen},
year = {2017},
doi = {10.1109/CCECE.2017.7946664},
url = {https://doi.org/10.1109/CCECE.2017.7946664},
researchr = {https://researchr.org/publication/YellaSS17},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {30th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2017, Windsor, ON, Canada, April 30 - May 3, 2017},
publisher = {IEEE},
isbn = {978-1-5090-5538-8},
}