Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty. STEP: a unified design methodology for secure test and IP core protection. In Erik Brunvard, Ken Stevens, Joseph R. Cavallaro, Tong Zhang 0002, editors, Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012. pages 333-338, ACM, 2012. [doi]
@inproceedings{YeolekarSMPM12,
title = {STEP: a unified design methodology for secure test and IP core protection},
author = {Pranav Yeolekar and Rishad A. Shafik and Jimson Mathew and Dhiraj K. Pradhan and Saraju P. Mohanty},
year = {2012},
doi = {10.1145/2206781.2206862},
url = {http://doi.acm.org/10.1145/2206781.2206862},
researchr = {https://researchr.org/publication/YeolekarSMPM12},
cites = {0},
citedby = {0},
pages = {333-338},
booktitle = {Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012},
editor = {Erik Brunvard and Ken Stevens and Joseph R. Cavallaro and Tong Zhang 0002},
publisher = {ACM},
isbn = {978-1-4503-1244-8},
}