Low power motion estimator architecture with leakage power reduction in deep sub-micron SoC - researchr publication authors

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Gyu-Sung Yeon, Chi-Hun Jun, Tae Jin Hwang, Seongsoo Lee, Jae-Kyung Wee. Low power motion estimator architecture with leakage power reduction in deep sub-micron SoC. In M. H. Rashid, editor, Proceedings of the Second IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, USA, November 28, 2004 - December 1, 2004. pages 85-89, IASTED/ACTA Press, 2004.

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