Gyu-Sung Yeon, Chi-Hun Jun, Tae Jin Hwang, Seongsoo Lee, Jae-Kyung Wee. Low power motion estimator architecture with leakage power reduction in deep sub-micron SoC. In M. H. Rashid, editor, Proceedings of the Second IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, USA, November 28, 2004 - December 1, 2004. pages 85-89, IASTED/ACTA Press, 2004.
@inproceedings{YeonJHLW04,
title = {Low power motion estimator architecture with leakage power reduction in deep sub-micron SoC},
author = {Gyu-Sung Yeon and Chi-Hun Jun and Tae Jin Hwang and Seongsoo Lee and Jae-Kyung Wee},
year = {2004},
tags = {architecture},
researchr = {https://researchr.org/publication/YeonJHLW04},
cites = {0},
citedby = {0},
pages = {85-89},
booktitle = {Proceedings of the Second IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, USA, November 28, 2004 - December 1, 2004},
editor = {M. H. Rashid},
publisher = {IASTED/ACTA Press},
}