Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation

Haibing Yin, Dong-Sun Park, Xiao-yun Zhang. Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation. J. Real-Time Image Processing, 11(3):507-525, 2016. [doi]

Authors

Haibing Yin

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Dong-Sun Park

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Xiao-yun Zhang

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