Jae Wook Yoo, Tae-Ho Kim, Dong-Kyun Kim, Jin-Ku Kang. A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2. In Thomas Büchner, Ramalingam Sridhar, Andrew Marshall, Norbert Schuhmann, editors, Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings. pages 88-91, IEEE, 2010. [doi]
@inproceedings{YooKKK10,
title = {A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2},
author = {Jae Wook Yoo and Tae-Ho Kim and Dong-Kyun Kim and Jin-Ku Kang},
year = {2010},
doi = {10.1109/SOCC.2010.5784642},
url = {http://dx.doi.org/10.1109/SOCC.2010.5784642},
researchr = {https://researchr.org/publication/YooKKK10},
cites = {0},
citedby = {0},
pages = {88-91},
booktitle = {Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings},
editor = {Thomas Büchner and Ramalingam Sridhar and Andrew Marshall and Norbert Schuhmann},
publisher = {IEEE},
isbn = {978-1-4244-6682-5},
}