Hyunchul Yoon, Teawoong Kim, Yigi Kwon, Youngcheol Chae. A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. In IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. pages 88-89, IEEE, 2022. [doi]
@inproceedings{YoonKKC22,
title = {A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier},
author = {Hyunchul Yoon and Teawoong Kim and Yigi Kwon and Youngcheol Chae},
year = {2022},
doi = {10.1109/VLSITechnologyandCir46769.2022.9830300},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830300},
researchr = {https://researchr.org/publication/YoonKKC22},
cites = {0},
citedby = {0},
pages = {88-89},
booktitle = {IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
publisher = {IEEE},
isbn = {978-1-6654-9772-5},
}