Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto. Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell. IEICE Transactions, 97-A(9):1945-1951, 2014. [doi]
@article{YoshimotoKY14,
title = {Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell},
author = {Shusuke Yoshimoto and Hiroshi Kawaguchi and Masahiko Yoshimoto},
year = {2014},
url = {http://search.ieice.org/bin/summary.php?id=e97-a_9_1945},
researchr = {https://researchr.org/publication/YoshimotoKY14},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {97-A},
number = {9},
pages = {1945-1951},
}