A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS - researchr publication authors

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Yang You, Sudipto Chakraborty, Rui Wang, Jinghong Chen. A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015. pages 1-4, IEEE, 2015. [doi]

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