A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS

Yang You, Sudipto Chakraborty, Rui Wang, Jinghong Chen. A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015. pages 1-4, IEEE, 2015. [doi]

@inproceedings{YouCWC15,
  title = {A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS},
  author = {Yang You and Sudipto Chakraborty and Rui Wang and Jinghong Chen},
  year = {2015},
  doi = {10.1109/ASSCC.2015.7387469},
  url = {http://dx.doi.org/10.1109/ASSCC.2015.7387469},
  researchr = {https://researchr.org/publication/YouCWC15},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015},
  publisher = {IEEE},
  isbn = {978-1-4673-7191-9},
}