A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS

Ramy Yousry, Henry Park, E.-Hung Chen, Chih-Kong Ken Yang. A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013. pages 2443-2447, IEEE, 2013. [doi]

@inproceedings{YousryPCY13,
  title = {A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS},
  author = {Ramy Yousry and Henry Park and E.-Hung Chen and Chih-Kong Ken Yang},
  year = {2013},
  doi = {10.1109/ISCAS.2013.6572373},
  url = {http://dx.doi.org/10.1109/ISCAS.2013.6572373},
  researchr = {https://researchr.org/publication/YousryPCY13},
  cites = {0},
  citedby = {0},
  pages = {2443-2447},
  booktitle = {2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013},
  publisher = {IEEE},
  isbn = {978-1-4673-5760-9},
}