FPGA interconnect design using logical effort - researchr publication

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Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong. FPGA interconnect design using logical effort. In FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008. pages 447-450, IEEE, 2008. [doi]

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