Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA

Tingting Yu, Lei Chen, Xuewu Li, Shuo Wang, Jing Zhou. Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA. In Proceedings of the 6th International Conference on Informatics, Environment, Energy and Applications, IEEA '17, Jeju, Republic of Korea, March 29-31, 2017. pages 112-116, ACM, 2017. [doi]

Abstract

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