Xiaobao Yu, Baoyong Chi, Meng Wei, Albert Z. Wang, Tianling Ren, Zhihua Wang. A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013. pages 962-965, IEEE, 2013. [doi]
@inproceedings{YuCWWRW13,
title = {A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS},
author = {Xiaobao Yu and Baoyong Chi and Meng Wei and Albert Z. Wang and Tianling Ren and Zhihua Wang},
year = {2013},
doi = {10.1109/ISCAS.2013.6572008},
url = {http://dx.doi.org/10.1109/ISCAS.2013.6572008},
researchr = {https://researchr.org/publication/YuCWWRW13},
cites = {0},
citedby = {0},
pages = {962-965},
booktitle = {2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013},
publisher = {IEEE},
isbn = {978-1-4673-5760-9},
}