Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 0002, Felice Balarin. Assertion-based power/performance analysis of network processor architectures. In Ninth IEEE International High-Level Design Validation and Test Workshop 2004, Sonoma Valley, CA, USA, November 10-12, 2004. pages 155-160, IEEE Computer Society, 2004. [doi]
@inproceedings{YuWCH0B04,
title = {Assertion-based power/performance analysis of network processor architectures},
author = {Jia Yu and Wei Wu and Xi Chen and Harry Hsieh and Jun Yang 0002 and Felice Balarin},
year = {2004},
doi = {10.1109/HLDVT.2004.1431261},
url = {http://doi.ieeecomputersociety.org/10.1109/HLDVT.2004.1431261},
researchr = {https://researchr.org/publication/YuWCH0B04},
cites = {0},
citedby = {0},
pages = {155-160},
booktitle = {Ninth IEEE International High-Level Design Validation and Test Workshop 2004, Sonoma Valley, CA, USA, November 10-12, 2004},
publisher = {IEEE Computer Society},
isbn = {0-7803-8714-7},
}