Kunzhi Yu, Ziqiang Wang, Xuan Ma, Xuqiang Zheng, Chun Zhang, Zhihua Wang. A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS. In 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012. pages 936-939, IEEE, 2012. [doi]
Abstract is missing.