17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs - researchr publication authors

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Won-Joo Yun, Indal Song, Hanki Jeoung, Hundai Choi, Seok Ho Lee, Jun-Bae Kim, Chi-Wook Kim, Jung Hwan Choi, Seong-Jin Jang, Joo-Sun Choi. 17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015. pages 1-3, IEEE, 2015. [doi]

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