Juliano C. Zanelli, Carolina Metzler, Ricardo Augusto da Luz Reis. Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits. In 11th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2020, San Jose, Costa Rica, February 25-28, 2020. pages 1-4, IEEE, 2020. [doi]
Abstract is missing.