A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing

Florian Zaruba, Fabian Schuiki, Luca Benini. A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. In IEEE Hot Chips 32 Symposium, HCS 2020, Palo Alto, CA, USA, August 16-18, 2020. pages 1-24, IEEE, 2020. [doi]

Authors

Florian Zaruba

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Fabian Schuiki

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Luca Benini

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