Florian Zaruba, Fabian Schuiki, Luca Benini. A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. In IEEE Hot Chips 32 Symposium, HCS 2020, Palo Alto, CA, USA, August 16-18, 2020. pages 1-24, IEEE, 2020. [doi]
@inproceedings{ZarubaSB20,
title = {A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing},
author = {Florian Zaruba and Fabian Schuiki and Luca Benini},
year = {2020},
doi = {10.1109/HCS49909.2020.9220474},
url = {https://doi.org/10.1109/HCS49909.2020.9220474},
researchr = {https://researchr.org/publication/ZarubaSB20},
cites = {0},
citedby = {0},
pages = {1-24},
booktitle = {IEEE Hot Chips 32 Symposium, HCS 2020, Palo Alto, CA, USA, August 16-18, 2020},
publisher = {IEEE},
isbn = {978-1-7281-7129-6},
}