A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors

Zhixiao Zhang, Jia-Jing Chen, Xin Si, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Yen-Cheng Chiu, Je-Min Hong, Shyh-Shyuan Sheu, Sih-Han Li, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang. A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macau, SAR, China, November 4-6, 2019. pages 217-218, IEEE, 2019. [doi]

@inproceedings{ZhangCSTSHWWCHS19,
  title = {A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors},
  author = {Zhixiao Zhang and Jia-Jing Chen and Xin Si and Yung-Ning Tu and Jian-Wei Su and Wei-Hsing Huang and Jing-Hong Wang and Wei-Chen Wei and Yen-Cheng Chiu and Je-Min Hong and Shyh-Shyuan Sheu and Sih-Han Li and Ren-Shuo Liu and Chih-Cheng Hsieh and Kea-Tiong Tang and Meng-Fan Chang},
  year = {2019},
  doi = {10.1109/A-SSCC47793.2019.9056933},
  url = {https://doi.org/10.1109/A-SSCC47793.2019.9056933},
  researchr = {https://researchr.org/publication/ZhangCSTSHWWCHS19},
  cites = {0},
  citedby = {0},
  pages = {217-218},
  booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macau, SAR, China, November 4-6, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-5106-9},
}