A 3 mW 1.2-3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth

Jili Zhang, Yu Li, Shengxi Diao, Xuefei Bai, Fujiang Lin. A 3 mW 1.2-3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth. Journal of Circuits, Systems, and Computers, 27(8):1-18, 2018. [doi]

Authors

Jili Zhang

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Yu Li

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Shengxi Diao

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Xuefei Bai

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Fujiang Lin

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