A 3 mW 1.2-3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth

Jili Zhang, Yu Li, Shengxi Diao, Xuefei Bai, Fujiang Lin. A 3 mW 1.2-3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth. Journal of Circuits, Systems, and Computers, 27(8):1-18, 2018. [doi]

Abstract

Abstract is missing.