Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Kiyoshi Yanagisawa, Junjun Qiu, Yun Wang, Jian Pang, Atsushi Shirane, Kenichi Okada. A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. In IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020. pages 1-2, IEEE, 2020. [doi]
@inproceedings{ZhangLGWYQWPSO20,
title = {A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL},
author = {Yuncheng Zhang and Bangan Liu and Xiaofan Gu and Chun Wang and Kiyoshi Yanagisawa and Junjun Qiu and Yun Wang and Jian Pang and Atsushi Shirane and Kenichi Okada},
year = {2020},
doi = {10.1109/VLSICircuits18222.2020.9162955},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162955},
researchr = {https://researchr.org/publication/ZhangLGWYQWPSO20},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020},
publisher = {IEEE},
isbn = {978-1-7281-9942-9},
}