An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

Jie Zhang, Dongming Zhou. An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA. IEEE T. Instrumentation and Measurement, 67(2):406-414, 2018. [doi]

Abstract

Abstract is missing.