A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS - researchr publication authors

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Zhao Zhang, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu. A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]

This author has not been identified. Look up 'Zhao Zhang' in GoogleThis author has not been identified. Look up 'Zhaoyu Zhang' in GoogleThis author has not been identified. Look up 'Yong Chen' in GoogleThis author has not been identified. Look up 'Nan Qi' in GoogleThis author has not been identified. Look up 'Jian Liu' in GoogleThis author has not been identified. Look up 'Nanjian Wu' in GoogleThis author has not been identified. Look up 'Liyuan Liu' in Google

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