2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE - researchr publication authors

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Zhaoyu Zhang, Zhao Zhang 0004, Yong Chen, Guoqing Wang, Xinyu Shen, Nan Qi, Guike Li, Shuangming Yu, Jian Liu, Nanjian Wu, Liyuan Liu. 2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE. In 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023. pages 177-180, IEEE, 2023. [doi]

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