Zhou Zhao, Xinlu Chen, Ashok Srivastava, Lu Peng, Saraju P. Mohanty. Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design. In 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017. pages 562-567, IEEE, 2017. [doi]
@inproceedings{ZhaoCSPM17,
title = {Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design},
author = {Zhou Zhao and Xinlu Chen and Ashok Srivastava and Lu Peng and Saraju P. Mohanty},
year = {2017},
doi = {10.1109/ISVLSI.2017.104},
url = {https://doi.org/10.1109/ISVLSI.2017.104},
researchr = {https://researchr.org/publication/ZhaoCSPM17},
cites = {0},
citedby = {0},
pages = {562-567},
booktitle = {2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017},
publisher = {IEEE},
isbn = {978-1-5090-6762-6},
}