Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert. Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. IEEE Trans. on Circuits and Systems, 61-I(2):443-454, 2014. [doi]
@article{ZhaoMDZPKBADMQRRC14,
title = {Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories},
author = {Weisheng Zhao and Mathieu Moreau and Erya Deng and Yue Zhang and Jean Michel Portal and Jacques-Olivier Klein and Marc Bocquet and Hassen Aziza and Damien Deleruyelle and Christophe Muller and Damien Querlioz and Nesrine Ben Romdhane and Dafine Ravelosona and Claude Chappert},
year = {2014},
doi = {10.1109/TCSI.2013.2278332},
url = {http://dx.doi.org/10.1109/TCSI.2013.2278332},
researchr = {https://researchr.org/publication/ZhaoMDZPKBADMQRRC14},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {61-I},
number = {2},
pages = {443-454},
}