Yuxiang Zheng, Jin Liu, Robert Payne, Mark Morgan, Hoi Lee. A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-$\mu{\rm m}$ CMOS. IEEE Trans. VLSI Syst., 21(12):2274-2285, 2013. [doi]
@article{ZhengLPML13,
title = {A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-$\mu{\rm m}$ CMOS},
author = {Yuxiang Zheng and Jin Liu and Robert Payne and Mark Morgan and Hoi Lee},
year = {2013},
doi = {10.1109/TVLSI.2012.2232319},
url = {http://dx.doi.org/10.1109/TVLSI.2012.2232319},
researchr = {https://researchr.org/publication/ZhengLPML13},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {21},
number = {12},
pages = {2274-2285},
}