Post-route LUT output polarity selection for timing optimization

Kai Zhu. Post-route LUT output polarity selection for timing optimization. In André DeHon, Mike Hutton, editors, Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007. pages 89-96, ACM, 2007. [doi]

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