Abstract is missing.
- A routing fabric for monolithically stacked 3D-FPGAMingjie Lin, Abbas El Gamal. 3-12 [doi]
- Design of a logic element for implementing an asynchronous FPGAScott C. Smith. 13-22 [doi]
- Designing efficient input interconnect blocks for LUT clusters using counting and entropyWenyi Feng, Sinan Kaptanoglu. 23-32 [doi]
- A synthesizable datapath-oriented embedded FPGA fabricSteven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton. 33-41 [doi]
- A versatile, low latency HyperTransport coreDavid Slogsnat, Alexander Giese, Ulrich Brüning. 45-52 [doi]
- An FPGA-based Pentium in a complete desktop systemShih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh. 53-59 [doi]
- A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGAEdward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen. 60-68 [doi]
- Variation-aware routing for FPGAsSatish Sivaswamy, Kia Bazargan. 71-79 [doi]
- Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variationYan Lin, Lei He. 80-88 [doi]
- Post-route LUT output polarity selection for timing optimizationKai Zhu. 89-96 [doi]
- Synthesis of an application-specific soft multiprocessor systemJason Cong, Guoling Han, Wei Jiang. 99-107 [doi]
- FPGA-friendly code compression for horizontal microcoded custom IPsBita Gorjiara, Daniel Gajski. 108-115 [doi]
- A practical FPGA-based framework for novel CMP researchSewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun. 116-125 [doi]
- High-level languages: the future or a passing fad?Michael J. Wirthlin, Misha Burich, Andrew Guyler, Brian Von Herzen. 127 [doi]
- Integrating FPGAs in high-performance computing: introductionPaul Chow, Mike Hutton. 131 [doi]
- Integrating FPGAs in high-performance computing: the architecture and implementation perspectiveNathan Woods. 132 [doi]
- Integrating FPGAs in high-performance computing: programming models for parallel systems -- the programmer s perspectiveSatnam Singh. 133-135 [doi]
- Improved SAT-based Boolean matching using implicants for LUT-based FPGAsJason Cong, Kirill Minkovich. 139-147 [doi]
- Power-aware FPGA logic synthesis using binary decision diagramsKevin Oo Tinmaung, David Howland, Russell Tessier. 148-155 [doi]
- GlitchLess: an active glitch minimization technique for FPGAsJulien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton. 156-165 [doi]
- Performance and yield enhancement of FPGAs with within-die variation using multiple configurationsYohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike. 169-177 [doi]
- Parametric yield in FPGAs due to within-die delay variations: a quantitative analysisN. Pete Sedcole, Peter Y. K. Cheung. 178-187 [doi]
- Efficient hardware checkpointing: concepts, overhead analysis, and implementationDirk Koch, Christian Haubelt, Jürgen Teich. 188-196 [doi]
- The shunt: an FPGA-based accelerator for network intrusion preventionNicholas Weaver, Vern Paxson, José M. González. 199-206 [doi]
- Attacking elliptic curve cryptosystems with special-purpose hardwareTim Güneysu, Christof Paar, Jan Pelzl. 207-215 [doi]
- CReconfigurable finite field instruction set architectureNathan Jachimiec, Fernando Martinez-Vallin, Jafar Saniie. 216-220 [doi]