A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Kezhen Zhu, Shunyu Li, Guangyong Chu. A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology. IEICE Electronic Express, 20:20220527, 2023. [doi]

@article{ZhuLC23,
  title = {A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology},
  author = {Kezhen Zhu and Shunyu Li and Guangyong Chu},
  year = {2023},
  doi = {10.1587/elex.19.20220527},
  url = {https://doi.org/10.1587/elex.19.20220527},
  researchr = {https://researchr.org/publication/ZhuLC23},
  cites = {0},
  citedby = {0},
  journal = {IEICE Electronic Express},
  volume = {20},
  pages = {20220527},
}