Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs

Jun Zhu, Ingo Sander, Axel Jantsch. Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010. pages 1035-1040, IEEE, 2010. [doi]

@inproceedings{ZhuSJ10,
  title = {Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs},
  author = {Jun Zhu and Ingo Sander and Axel Jantsch},
  year = {2010},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5456962},
  tags = {design},
  researchr = {https://researchr.org/publication/ZhuSJ10},
  cites = {0},
  citedby = {0},
  pages = {1035-1040},
  booktitle = {Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010},
  publisher = {IEEE},
}