The following publications are possibly variants of this publication:
- Low-latency Hardware Architecture for VDF Evaluation in Class GroupsDanyang Zhu, Jing Tian 0004, Minghao Li, Zhongfeng Wang. iacr, 2022:755, 2022. [doi]
- A High-Speed Architecture for the Reduction in VDF Based on a Class GroupYifeng Song, Danyang Zhu, Jing Tian 0004, Zhongfeng Wang. iacr, 2021:949, 2021. [doi]
- A High-Speed Architecture for the Reduction in VDF Based on a Class GroupYifeng Song, Danyang Zhu, Jing Tian 0004, Zhongfeng Wang. socc 2020: 147-152 [doi]