Table of Contents

• HARDY: Hardware based Analysis for malwaRe Detection in embedded sYstemsSai Praveen Kadiyala, Mohit Garg, Manaar Alam, Hau T. Ngo, Debdeep Mukhopadhyay, Thambipillai Srikanthan. 1-6 [doi]
• A Reconfigurable Permutation Based Address Encryption Architecture for Memory SecurityYuchen Mei, Li Du, Xuewen He, Yuan Du, Xiaoliang Chen, Zhongfeng Wang. 7-12 [doi]
• Evolution of Embedded Platform Security Technologies: Past, Present & Future ChallengesFahad Siddiqui, Sakir Sezer. 13-18 [doi]
• A Low-Cost Fault Injection Attack Resilient FSM DesignZiming Wang, Aijiao Cui, Gang Qu. 19-24 [doi]
• FPGA Based Co-design of Storage-side Query Filter for Big Data SystemsJinyu Zhan, Ying Li, Wei Jiang, Jianping Zhu. 25-30 [doi]
• Architectural Exploration on Racetrack MemoriesRui Xu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Liang Shi, Shouzhen Gu. 31-36 [doi]
• A DNN Compression Framework for SOT-MRAM-based Processing-In-Memory EngineGeng Yuan, Xiaolong Ma, Sheng Lin, Zhengang Li, Jieren Deng, Caiwen Ding. 37-42 [doi]
• Cube Attack on a Trojan-Compromised Hardware Implementation of AsconBasel Halak, Jorge Duarte-Sanchez. 43-47 [doi]
• The IANET Hardware Accelerator for Audio and Visual Data ClassificationRohini J. Gillela, Amlan Ganguly, Dorin Patru, Mark Indovina. 48-53 [doi]
• An Energy-Efficient Low Power LSTM Processor for Human Activity MonitoringArnab Neelim Mazumder, Hasib-Al-Rashid, Tinoosh Mohsenin. 54-59 [doi]
• Self-Correcting Op-Amp Input Offset Using Analog Floating GatesSai Govinda Rao Nimmalapudi, Andrew Marshall, Harvey Stiegler, Keith Jarreau. 60-65 [doi]
• Cycle-to-cycle Variation Enabled Energy Efficient Privacy Preserving Technology in ANNJingyan Fu, Zhiheng Liao, Jinhui Wang. 66-71 [doi]
• Improving the Performance of a NoC-based CNN Accelerator with Gather SupportBinayak Tiwari, Mei Yang, Xiaohang Wang, Yingtao Jiang, Venkatesan Muthukumar. 72-77 [doi]
• A Novel Method for Hardware Acceleration of Convex Hull Algorithm on Reconfigurable HardwareKris Min, Brenda Ly, Joshua Garner, Shahnam Mirzaei. 78-83 [doi]
• Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the TransformerSiyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang. 84-89 [doi]
• Optimizing CNN Accelerator With Improved Roofline ModelShaoxia Fang, Shulin Zeng, Yu Wang 0002. 90-95 [doi]
• A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural NetworksTaha Soliman, Ricardo Olivo, Tobias Kirchner, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn. 96-101 [doi]
• End-to-end Scalable and Low Power Multi-modal CNN for Respiratory-related Symptoms DetectionHaoran Ren, Arnab Neelim Mazumder, Hasib-Al-Rashid, Vandana Chandrareddy, Aidin Shiri, Nitheesh Kumar Manjunath, Tinoosh Mohsenin. 102-107 [doi]
• Analog Content Addressable Memory using Ferroelectric: A Case Study of Search-in-MemoryChuangtao Chen, Qingrong Huang, Chao L, Li Zhang, Cheng Zhuo, Xunzhao Yin. 108-112 [doi]
• 2IM: A Compact Computing-In-Memory Unit of 10 Transistors with Standard 6T SRAMErxiang Ren, Li Luo, Zheyu Liu, Fei Qiao, Qi Wei 0001. 113-116 [doi]
• Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and LatencyLi Yang, Zhezhi He, Shaahin Angizi, Deliang Fan. 117-122 [doi]
• Deep Learning Acceleration using Digital-Based Processing In-MemoryMohsen Imani, Saransh Gupta, Yeseong Kim, Tajana Rosing. 123-128 [doi]
• Switched Capacitor Based Area Efficient Voltage Quadruple for High Pumping EfficiencyVikas Rana, Shivam Kalla. 129-134 [doi]
• Mist-Scan: A Secure Scan Chain Architecture to Resist Scan-Based Attacks in Cryptographic ChipsMohammad Taherifard, Hakem Beitollahi, Fateme Jamali, Amin Norollah, Ahmad Patooghy. 135-140 [doi]
• DVFS Considering Spatial Correlation Timing and Process-Voltage-Temperature VariationsTung-Liang Lin, Sao-Jie Chen. 141-146 [doi]
• A High-Speed Architecture for the Reduction in VDF Based on a Class GroupYifeng Song, Danyang Zhu, Jing Tian 0004, Zhongfeng Wang. 147-152 [doi]
• An Inverter-based On-chip Voltage Reference Generator for Low Power ApplicationYuchen Zhao, Zhuo Zou, Lirong Zheng 0001. 153-157 [doi]
• Downlink-Centric User Scheduling for Full-Duplex MU-MIMO SystemsJianhua Zhang, Ming Zou, Lai Wei, Meng Ma, Bingli Jiao. 158-162 [doi]
• An Ultra-Low Power 900 MHz Intermediate Frequency Low Noise Amplifier For Low-Power RF ReceiversAasish Boora, Bharatha Kumar Thangarasu, Kiat Seng Yeo. 163-167 [doi]
• Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGAXiao Wu, Yufei Ma, Zhongfeng Wang. 168-173 [doi]
• A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured SparsityShouliang Guo, Chao Fang, Jun Lin, Zhongfeng Wang. 174-179 [doi]
• Dynamic Precision Multiplier For Deep Neural Network AcceleratorsChen Ding, Yuxiang Huan, Lirong Zheng 0001, Zhuo Zou. 180-184 [doi]
• Deep Reinforcement Learning for Self-Configurable NoCMd Farhadur Reza. 185-190 [doi]
• Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D IntegrationIvan Miketic, Emre Salman. 191-194 [doi]
• Efficient Metal Inter-Layer Via Utilization Strategies for Three-dimensional Integrated CircuitsUmamaheswara Rao Tida, Madhava Sarma Vemuri. 195-200 [doi]
• Achieving Flexible, Low-Latency and 100Gbps Line-rate Load Balancing over Ethernet on FPGAJinyu Xie, Wenbo Yin, Lingli Wang. 201-206 [doi]
• FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAsJia-Bao Gao, Jian Wang, Md Tanvir Arafin, Jin-mei Lai. 207-212 [doi]
• Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAsJhanani Thiagarajan, Arnab A. Purkayastha, Atul Patil, Hamed Tabkhi. 213-218 [doi]
• Fine Grained Control Flow Checking with Dedicated FPGA MonitorsAugusto W. Hoppe, Jürgen Becker 0001, Fernanda Lima Kastensmidt. 219-224 [doi]
• Hybrid Stochastic Computing Circuits in Continuous Statistics DomainRenyuan Zhang, Tati Erlina, Tinh Van Nguyen, Yasuhiko Nakashima. 225-230 [doi]
• A Sub-1 ppm/°C CMOS Bandgap Voltage Reference With Process Tolerant Piecewise Second-Order Curvature CompensationYongjoon Ahn, Suhwan Kim, Hyunjoong Lee. 231-235 [doi]
• Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance RegionShoya Sonoda, Jun Shiomi, Hidetoshi Onodera. 236-241 [doi]
• Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICsPo-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang, Hung-Ming Chen. 242-247 [doi]
• Secure Your SoC: Building System-an-Chip Designs for SecurityShivam Bhasin, Trevor E. Carlson, Anupam Chattopadhyay, Vinay B. Y. Kumar, Avi Mendelson, Romain Poussier, Yaswanth Tavva. 248-253 [doi]
• Simultaneous Multi Voltage Aware Timing Analysis Methodology for SOC using Machine LearningVishant Gotra, Srinivasa Kodanda Rama Reddy. 254-257 [doi]
• Optimized Power Grid Planning for Enabling Low Power Features for Leakage Power Reduction in SOCVishant Gotra, Srinivasa Kodanda Rama Reddy, Tanniru Srinivasa Rao, Pavithra P. 258-261 [doi]
• ASIC Power Estimation Across Revisions using Machine LearningAli Tariq, Howard Yang. 262-264 [doi]
• AutoML for Multilayer Perceptron and FPGA Co-designPhilip Colangelo, Oren Segal, Alexander Speicher, Martin Margala. 265-266 [doi]
• Programmable Voltage Reference Circuit Using an Analog Floating Gate DeviceSai Nimmalapudi, Harvey Stiegler, Andrew Marshall, Keith Jarreau. 267-270 [doi]
• A Dynamic Expansion Order Algorithm for the SAT-based MinimizationChia-Chun Lin, Kit Seng Tam, Chana-Cheng Ko, Hsin-Ping Yen, Shenz-Hsiu Wei, Yung-Chih Chen, Chun-Yao Wang. 271-276 [doi]
• Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case StudyM. D. Arafat Kabir, Yarui Peng. 277-282 [doi]
• A SpaceWire PHY with Double Data Rate and Fallback RedundancyMong Tee Sim, Yanyan Zhuang. 283-288 [doi]