Danfeng Zhu, Rui Wang, Hui Wang, Depei Qian, Zhongzhi Luan, Tianshu Chu. A Fair Thread-Aware Memory Scheduling Algorithm for Chip Multiprocessor. In Ching-Hsien Hsu, Laurence Tianruo Yang, Jong Hyuk Park, Sang-Soo Yeo, editors, Algorithms and Architectures for Parallel Processing, 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings. Part I. Volume 6081 of Lecture Notes in Computer Science, pages 174-185, Springer, 2010. [doi]
@inproceedings{ZhuWWQLC10,
title = {A Fair Thread-Aware Memory Scheduling Algorithm for Chip Multiprocessor},
author = {Danfeng Zhu and Rui Wang and Hui Wang and Depei Qian and Zhongzhi Luan and Tianshu Chu},
year = {2010},
doi = {10.1007/978-3-642-13119-6_15},
url = {http://dx.doi.org/10.1007/978-3-642-13119-6_15},
tags = {context-aware},
researchr = {https://researchr.org/publication/ZhuWWQLC10},
cites = {0},
citedby = {0},
pages = {174-185},
booktitle = {Algorithms and Architectures for Parallel Processing, 10th International Conference, ICA3PP 2010, Busan, Korea, May 21-23, 2010. Proceedings. Part I},
editor = {Ching-Hsien Hsu and Laurence Tianruo Yang and Jong Hyuk Park and Sang-Soo Yeo},
volume = {6081},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-642-13118-9},
}