A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only) - researchr publication authors

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Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan. A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). In John Wawrzynek, Katherine Compton, editors, Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011. pages 281, ACM, 2011. [doi]

This author has not been identified. Look up 'Jianfeng Zhu' in GoogleThis author has not been identified. Look up 'Dong Wu' in GoogleThis author has not been identified. Look up 'Yaru Yan' in GoogleThis author has not been identified. Look up 'Xiao Yu' in GoogleThis author has not been identified. Look up 'Hu He' in GoogleThis author has not been identified. Look up 'Liyang Pan' in Google

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