Abstract is missing.
- The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshopJonathan Rose, Guy G. Lemieux. 1-2 [doi]
- Should the academic community launch an open-source FPGA device and tools effort?: evening panelJohn Wawrzynek. 3-4 [doi]
- Comparing FPGA vs. custom cmos and the impact on processor microarchitectureHenry Wong, Vaughn Betz, Jonathan Rose. 5-14 [doi]
- VEGAS: soft vector processor with scratchpad memoryChristopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G. Lemieux. 15-24 [doi]
- Leap scratchpads: automatic memory and cache management for reconfigurable logicMichael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer. 25-28 [doi]
- NetTM: faster and easier synchronization for soft multicores via transactional memoryMartin Labrecque, J. Gregory Steffan. 29-32 [doi]
- LegUp: high-level synthesis for FPGA-based processor/accelerator systemsAndrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski. 33-36 [doi]
- Automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAsLing Liu, Oleksii Morozov, Yuxing Han, Jürg Gutknecht, Patrick R. Hunziker. 37-40 [doi]
- Torc: towards an open-source tool flowNeil Steiner, Aaron Wood, Hamid Shojaei, Jacob Couch, Peter Athanas, Matthew French. 41-44 [doi]
- FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sortingDirk Koch, Jim Torresen. 45-54 [doi]
- Real-time high-definition stereo matching on FPGALu Zhang 0018, Ke Zhang, Tian-Sheuan Chang, Gauthier Lafruit, Georgi Krasimirov Kuzmanov, Diederik Verkest. 55-64 [doi]
- Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migrationHaohuan Fu, Robert G. Clapp. 65-74 [doi]
- A platform for high level synthesis of memory-intensive image processing algorithmsTim Papenfuss, Holger Michel. 75-78 [doi]
- Improved double angle complex rotation QRD-RLSQiang Gao, Robert W. Stewart. 79-82 [doi]
- Authenticated encryption for FPGA bitstreamsSteven Trimberger, Jason Moore, Weiguang Lu. 83-86 [doi]
- A 65nm flash-based FPGA fabric optimized for low cost and powerJonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner. 87-96 [doi]
- CoRAM: an in-fabric memory architecture for FPGA-based computingEric S. Chung, James C. Hoe, Ken Mai. 97-106 [doi]
- Energy-efficient specialization of functional units in a coarse-grained reconfigurable arrayBrian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck. 107-110 [doi]
- Thermal and power characterization of field-programmable gate arraysAbdullah Nazma Nowroz, Sherief Reda. 111-114 [doi]
- DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture researchJuergen Ributzka, Yuhei Hayashi, Fei Chen, Guang R. Gao. 115-118 [doi]
- Bridging the GPGPU-FPGA efficiency gapChristopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek. 119-122 [doi]
- A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elementsDavid Grant, Chris Wang, Guy G. Lemieux. 123-132 [doi]
- Line-level incremental resynthesis techniques for FPGAsDoris Chen, Deshanand Singh. 133-142 [doi]
- Towards scalable FPGA CAD through architectureScott Y. L. Chin, Steven J. E. Wilton. 143-152 [doi]
- Scalable and deterministic timing-driven parallel placement for FPGAsChris C. Wang, Guy G. Lemieux. 153-162 [doi]
- Improved delay measurement method in FPGA based on transition probabilityJustin S. Wong, Peter Y. K. Cheung. 163-172 [doi]
- Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinderRaphael Rubin, André DeHon. 173-176 [doi]
- Performance estimation framework for automated exploration of CPU-accelerator architecturesTobias Kenter, Christian Plessl, Marco Platzner, Michael Kauschke. 177-180 [doi]
- An analytical model relating FPGA architecture parameters to routabilityJoydip Das, Steven J. E. Wilton. 181-184 [doi]
- The RLOC is dead - long live the RLOCSatnam Singh. 185-188 [doi]
- Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPICharles Lo, Paul Chow. 189-198 [doi]
- A monte-carlo floating-point unit for self-validating arithmeticJackson H. C. Yeung, Evangeline F. Y. Young, Philip Heng Wai Leong. 199-208 [doi]
- An FPGA implementation of a sparse quadratic programming solver for constrained predictive controlJuan Luis Jerez, George A. Constantinides, Eric C. Kerrigan. 209-218 [doi]
- Exploration of FPGA interconnect for the design of unconventional antennasAbhay Tavaragiri, Jacob Couch, Peter Athanas. 219-226 [doi]
- Architecture description and packing for logic blocks with hierarchy, modes and complex interconnectJason Luu, Jason Helge Anderson, Jonathan Rose. 227-236 [doi]
- Reducing the pressure on routing resources of FPGAs with generic logic chainsHadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne. 237-246 [doi]
- Co-synthesis of FPGA-based application-specific floating point simd acceleratorsAndrei Hagiescu, Weng-Fai Wong. 247-256 [doi]
- Memory-efficient and scalable virtual routers using FPGAHoang Le, Thilan Ganegedara, Viktor K. Prasanna. 257-266 [doi]
- FPGA side-channel receiversJi Sun, Ray Bittner, Ken Eguro. 267-276 [doi]
- Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only)Daniel Schinke, Wallace Shep Pitts, Neil Di Spigna, Paul Franzon. 277 [doi]
- An accelerated and energy-efficient traffic monitor using the NetFPGA (abstract only)Alfio Lombardo, Diego Reforgiato Recupero, Giovanni Schembra. 277 [doi]
- Resolving implicit barrier synchronizations in FPGA HLS (abstract only)Jason Cong, Yi Zou. 278 [doi]
- On timing yield improvement for FPGA designs using architectural symmetry (abstract only)Haile Yu, Qiang Xu, Philip Heng Wai Leong. 278 [doi]
- High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only)Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis. 278 [doi]
- A prototype FPGA for subthreshold-optimized CMOS (abstract only)Peter Grossmann, Miriam Leeser. 279 [doi]
- Fault modeling and characteristics of SRAM-based FPGAs (abstract only)Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He. 279 [doi]
- A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only)Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk. 281 [doi]
- A streaming FPGA implementation of a steerable filter for real-time applications (abstract only)Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan. 281 [doi]
- A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan. 281 [doi]
- Using many-core architectural templates for FPGA-based computing (abstract only)Mingjie Lin, Shaoyi Cheng, John Wawrzynek. 281 [doi]
- Variation tolerant asynchronous FPGA (abstract only)Hock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev. 282 [doi]
- FPGA-based fine-grain parallel computing (abstract only)Andrew W. Hill, Andrea Di Blas, Richard Hughey. 283 [doi]
- Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only)Somnath Paul, Swarup Bhunia. 283 [doi]
- Microblaze: an application-independent fpga-based profiler (abstract only)Fadi Obeidat, Robert H. Klenke. 283 [doi]
- Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only)Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung. 284 [doi]
- FPGA placement by graph isomorphism (abstract only)Hossein Omidian Savarbaghi, Kia Bazargan. 284 [doi]
- FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only)Yu Cai, Erich F. Haratsch, Mark McCartney, Mudit Bhargava, Ken Mai. 284 [doi]
- Regular fabric for regular FPGA (abstract only)Xun Chen, Jianwen Zhu. 284 [doi]
- Towards automated optimisation of tool-generated HW/SW sopc designs (abstract only)Ravikesh Chandra, Oliver Sinnen. 285 [doi]
- BBFEX: a bloom-bloomier filter extension for long patterns in FPGA-based pattern matching system (abstract only)Trung Hieu Bui, Duy Anh Tuan Nguyen, Ngoc Thinh Tran. 285 [doi]