Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski. A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO. In Vojin G. Oklobdzija, editor, Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, Marina del Rey, CA, USA, October 24-26, 2005. pages 128-131, IASTED/ACTA Press, 2005.
Abstract is missing.